Design D Latch and D Flip Flop Using Multiplexer
In this article, we will learn to
- Describe the D-flip flop using the three levels of abstraction – Gate level, Dataflow, and behavioral modeling.
- Generate the RTL schematic for the D flip flop.
- Write the testbench.
- Generate simulated waveforms.
What is D flip flop?
A flip flop can store one bit of data. Hence, it is known as a memory cell. Flip-flops are synchronous circuits since they use a clock signal. Using flip flops, we build complex circuits such as RAMs, Shift Registers, etc.
A D flip-flop stands for data or delay flip-flop. The outputs of this flip-flop are equal to the inputs.
As we proceed, we will see how we can design a D flip flop using different levels of abstraction
Gate level modeling
Gate level modeling uses primitive gates available in Verilog to build circuits. Hence, we need to know the logic diagram of the circuit we want to design.
From the above circuit, we can see that we need four NAND gates and one NOT gate to construct a D-flip flop in gate-level modeling.
Gate level Modeling of D flip flop
As always, the module is declared listing the terminal ports in the logic circuit.
module d_ff_gate(q,qbar,d,clk);
Note that we declare outputs first followed by inputs since built-in gates also follow the same pattern. Now, let's declare the input and output ports.
input d,clk; output q, qbar;
Clear Input in Flip flop
All hardware systems should have a pin to clear everything and have a fresh start. It applies to flip flops too. Hence, we will include a clear pin that forces the flip flop to a state where Q = 0 and Q' = 1 despite whatever input we provide at the D input. This clear input becomes handy when we tie up multiple flip flops to build counters, shift registers, etc.
Behavioral Modeling of D flip flop with Synchronous Clear
For synchronous clear, the output will reset at the triggered edge(positive edge in this case) of the clock after the clear input is activated.
Here's the code:
module dff_behavioral(d,clk,clear,q,qbar); input d, clk, clear; output reg q, qbar; [email protected](posedge clk) begin if(clear== 1) q <= 0; qbar <= 1; else q <= d; qbar = !d; end endmodule
Behavioral Modeling of D flip flop with Asynchronous Clear
For asynchronous clear, the clear signal is independent of the clock. Here, as soon as clear input is activated, the output reset.
This can be achieved by adding a clear signal to the sensitivity list. Hence we write our code as:
module dff_behavioral(d,clk,clear,q,qbar); input d, clk, clear; output reg q, qbar; [email protected](posedge clk or posedge clear) begin if(clear== 1) q <= 0; qbar <= 1; else q <= d; qbar = !d; end endmodule
Structural Modeling
Like in Gate level modeling, we analyze the logic design for structural modeling. We will consider the gates required to build the design. But, instead of using in-built gates, we take each gate and create separate modules that will be integrated to form the whole circuitry.
In the case of D-flip flop, we have a NOT and four NAND gates that build the circuit.
Hence, we have to structurize each gate with their respective module.
Structural Modeling of D flip flop
To start with code, we will first structurize the NAND gate.
We declare the module as nand_gate. The input and output ports are then declared.
module nand_gate(c,a,b); input a,b; output c;
Then, we use assign statement to write the logical expression for NAND.
assign c= ~(a & b);
The endmodule keyword is used for representing the end of the module.
Similarly, we do for NOT gate
module not_gate(f,e); input e; output f; assign f = ~e; endmodule
Note: We keep variables for assigning inputs and outputs in one module different from others. This ensures mixing up of signals does not happen during a simulation.
Now, we have to integrate these lower modules to form our D-flip flop. In order to do that, we use module instantiation. First, start with the name of the lower hierarchy module (defined and declared above) and write the name of the instance of your choice. The port-list will contain the output signals, followed by the input ones.
For example,
nand_gate nand1(x,clk,d);
Here,
- module-name :- nand_gate
- instance name:- nand1
- output port:- x(intermediate signal)
- input ports:- d and clk
Do the same for the rest of the instances
not_gate not1(dbar,d); nand_gate nand1(x,clk,d); nand_gate nand2(y,clk,dbar); nand_gate nand3(q,qbar,y); nand_gate nand4(qbar,q,x); endmodule
Hence, the final structure code will be:
module nand_gate(c,a,b); input a,b; output c; assign c = ~(a&b); endmodule module not_gate(f,e); input e; output f; assign f= ~e; endmodule module d_ff_struct(q,qbar,d,clk); input d,clk; output q, qbar; not_gate not1(dbar,d); nand_gate nand1(x,clk,d); nand_gate nand2(y,clk,dbar); nand_gate nand3(q,qbar,y); nand_gate nand4(qbar,q,x); endmodule
Testbench
A testbenchis an HDL module that is used to test another module, called thedevice under test (DUT). The test bench contains statements to apply inputs to the DUT and, ideally, to check that the correct outputs are produced. The input and desired output patterns are called test vectors.
Let's see how we can write a test bench for D-flip flop by following step by step instruction
//test bench for d flip flop //1. Declare module and ports module dff_test; reg D, CLK,reset; wire Q, QBAR; //2. Instantiate the module we want to test. We have instantiated the dff_behavior dff_behavior dut(.q(Q), .qbar(QBAR), .clear(reset), .d(D), .clk(CLK)); // instantiation by port name. //3. Monitor TB ports $monitor("simtime = %g, CLK = %b, D = %b,reset = %b, Q = %b, QBAR = %b", $time, CLK, D, reset, Q, QBAR); //4. apply test vectors initial begin clk=0; forever #10 clk = ~clk; end initial begin reset=1; D <= 0; #100; reset=0; D <= 1; #100; D <= 0; #100; D <= 1; end endmodule RTL Schematic
Here's how the RTL Schematic will look if we peek into the elaborate design of the behavioral model of the D-flip flop without clear input.
With synchronous clear input,
And with asynchronous clear input,
Simulated Waveforms
D flip flop Without Reset
In this waveform, we can see that the Q and Q' will be reset state at the positive cycle after clear is activated
In this waveform, we can see that the Q and Q' will be in the reset state as soon as clear is activated.
I hope you understood the implementation of a D flip-flop using the various modeling styles in Verilog. For any queries, leave us a comment below.
About the author
Aiysha is a 2019 BTech graduate in the field of Electronics and Communication from the College of Engineering, Perumon. Her fascination with digital circuit modeling encouraged her to pursue a PG diploma in VLSI and Embedded Hardware Design from NIELIT, Calicut. And this is where she was initiated into the world of Hardware Description and Verilog. She spends her downtime perfecting either her dance moves or her martial arts skills.
Design D Latch and D Flip Flop Using Multiplexer
Source: https://technobyte.org/verilog-code-d-flip-flop-dataflow-gate-behavioral/
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